The escalating demands for high densification and performance associated with ultra-large scale integration semiconductor devices require design features of about 0.25 microns and under, such as about 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a substrate, typically a semiconductor substrate comprising doped monocrystalline silicon, with contacts formed in the first dielectric layer for electrical connection with an active region on the substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, typically by sputter deposition. Aluminum and aluminum alloy layers are typically sputter deposited at a temperature of about 50 to about 500.degree. C. A photoresist mask is then formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features. A second dielectric layer, such as spin-on-glass (SOG) or hydrogen silsesquioxane (HSQ), is deposited to fill the gaps between the metal features. A third dielectric layer, e.g., oxide layer, such as silicon dioxide derived from tetraethyl orthosilicate (TEOS) by plasma enhanced chemical vapor deposition (PECVD) or silicon dioxide derived from silane by PECVD, is then deposited and planarized as by chemical mechanical polishing (CMP). A mask, e.g., a photoresist mask, is then formed on the third dielectric layer and a through-hole is formed in the second and third dielectric layers, as by anisotropic etching, to expose the underlying first metal feature. The through-hole can be formed such that the underlying first metal feature encloses the entire bottom opening thereof, serving as a landing pad for a metal plug filling the through-hole to form the conductive via. Prior to filling the through-hole, the photoresist mask is stripped, as by employing a combination of an oxygen plasma, is and solvent cleaning, all at elevated temperatures. A barrier metal is then deposited lining the through-hole in contact with the underlying metal feature to provide adhesion between the underlying metal feature and the subsequently deposited metal plug, such as tungsten typically vapor deposited by employing tungsten hexafluoride as a reactant gas.
The reduction in design features to about 0.25 microns and under requires extremely high densification which mandates high aspect ratio (height/width) openings. The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to escalating high densification requirements. It is also extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratios, e.g., in excess of four. Accordingly, conventional approaches also comprise purposely widening the diameter of the through-hole to decrease the aspect ratio which results in misalignment wherein upon the surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a "borderless via," which also conserves the chip real estate.
In forming either conventional landing pad vias or borderless vias, the via opening or through-hole is often designed to stop on a barrier layer formed on the underlying metal layer. Such a barrier layer typically comprises titanium nitride (TiN) which is formed on the underlying aluminum or aluminum alloy layer. However, the TiN layer is etched through or thinned during via etching, thereby exposing the underlying aluminum or aluminum alloy. Upon exposing the chip to higher temperatures during subsequent processing, as during plasma stripping of the photoresist, solvent cleaning, degassing and barrier metal or tungsten deposition, stress is induced which causes the aluminum or aluminum alloy to extrude up through the via through-hole, thereby creating killer defects.
Accordingly, there exists a need for a semiconductor methodology for forming reliable interconnections, particularly interconnections involving underlying aluminum or aluminum alloy features. There exists a particular need for reliable interconnection technology involving underlying aluminum or aluminum alloy features of about 0.50 microns and under.